DDS stands for Direct Digital Synthesis, is a digitally controlled technique of producing multiple frequencies from a reference clock source by creating a time-dependent varying signal and then converting the generated digital signal to analog. Since operations inside DDS devices are basically digital it can offer high-speed switching, fine resolution and operation over a wide range of output frequencies. With advanced new technology in design and process innovation, the present DDS devices are extremely minimal and draw little power.In the basic model of DDS, a programmable read-only memory (PROM) is driven by a stable clock source of a fixed frequency for storing at least one or more number of cycles of a sine wave (or another subjective waveform). Each memory location is driven by a Digital to Analog Converter (DAC) which helps in generating an analog signal. When the address counter passes through each location of the memory, the digital amplitude of the corresponding signal is converted to analog waveform or signal. The output signal purity depends on the DAC and the phase noise of the signal is the reference clock. The block diagram of a fundamental DDS system is shown in DDS is a system of sampled data, so every issue associated with sampling must be taken into consideration such as aliasing, filtering, quantization noise and so on. For example, the output frequencies of the DAC contain higher order harmonics which overlay with the Nyquist bandwidth and making the signal unfilterable. But in case of the phase locked loop (PLL) the higher order harmonics of the output signal are filterable.A major problem with the simple DDS system is changing the frequency of the output signal by changing either the frequency of the reference clock or by rewriting the PROM. This makes the fundamental DDS system rather inflexible. To overcome this, the practical DDS system executes in a substantially more adaptable and effective way utilizing digitally advanced equipment called as Numerically Controlled Oscillator (NCO). The block diagram of the practical DDS system is shown in Phase accumulator is the heart of the system, which means the phase to amplitude converter and a DAC. Depending on the reference clock frequency and the binary number written to the frequency register, a DDS generates a signal of a particular frequency. The primary input of the phase accumulator is the binary number programmed to the frequency register called “Tuning Word” and indicated with a symbol “M”. The content of the phase accumulator is updated for each and every clock cycle. Whenever the phase accumulator is updated, the M value in the delta phase register will be added to the register of the phase accumulator. The output of phase accumulator will process the address to the corresponding wave lookup table. Let’s suppose a sine look-up table is utilized, the phase accumulator processes the address of the phase for the lookup table, which in turn gives a digital value of the relating sine amplitude and phase angle to DAC. The DAC, thus, changes over that number to an equivalent value of analog voltage. At each clock cycle, a constant value is added to the phase accumulator in order to generate a fixed frequency output sine wave. Depending on the phase increment change such as large or small, the steps taken by the phase accumulator through the lookup table vary, generating a smaller or higher frequency sine wave.2.3. PHASE ACCUMULATOR: In DDS implementation, the phase accumulator seems to be like a phase Wheel. For a better understanding of the basic functionality, consider the sine wave oscillation to a vector rotating around the phase circle as shown in figure 2.3. Each assigned point on the phase wheel is equivalent to the proportional point of a sine wave cycle. As the vector turns around the wheel, the angle generates a sine wave corresponding to it. One full rotation of the vector around the wheel, at a steady speed, generates one complete cycle of the sine wave. The phase accumulator is the one which is responsible for giving equal angular values to the vector while rotating around the phase wheel.Phase accumulator is nothing but a counter, which keeps on increasing the number stored in it whenever a clock pulse is received. The size of the increment is controlled by the binary coded number (M). This decides how many phase steps need to be taken in between the reference clock. It adequately sets the number of points to skip in the phase wheel. The bigger the step size, the quicker is the overflow of the phase accumulator and faster the completion of the sine wave full cycle. The resolution of the Phase accumulator (n) determines the number of discrete points on the phase wheel. For example, let us consider n value is 32(n = 32) and M value is 1(M= 1), here the phase accumulator overflows 232 times and restarts again. The frequency output of sine wave is the clock frequency divided by 232. For suppose, if the value of the M = 2, then the accumulator overflows twice as faster than the previous one and the frequency of the generated output sine wave is double the actual frequency. The frequency of the output signal is calculated by the equation ( 2.1). The number of samples per cycle decreases as the frequency increases. According to sampling theory to reconstruct an output waveform it requires minimum two samples per cycle. Based on that, the DDS maximum output frequency is (Fc/2). But in practical applications, the frequency is less than (Fc/2) for allowing filtering of the output signal.