Before going to basic pipelining, it is required to review how an
unpipelined version of MIPS is implemented.
Five clock cycles are what is needed to implement one MIPS
instruction. These five cycles are:
1) Instruction fetch “IF”.
2) Instruction register/decoder fetch cycle “ID”.
3) Execution/effective address cycle “EX”.
4) Memory access/branch completion cycle “MEM”.
5) Write-back cycle “WB”.
In the end of every clock cycle, all values that are needed on a
later clock cycle and that is calculated during that clock cycle is put into a
temporary register (TR). The TR keeps values between clock cycles for one
instruction, meanwhile values between sequential instructions are stored in
other storage elements that are visible. This implementation is represented in
figure B.1. It is important to know that this implementation is what was used
in earlier times, while now complex processors use microcode.
Data path of figure B.1 can be pipelined by adding state registers,
these registers serve as kind of a partition that separate each of the five
steps of any kind of an instruction. Each of these state registers will be
named by the two steps that they are separating. They will be named IF/ID,
ID/EX, EX/MEM, and MEM/WB. These states registers can be seen in figure B.2.
These state registers were added to store values passed from one
stage to the following stage. They carry both control and data from one stage
to the following stage. All values that are needed on an upcoming stage must be
kept in the state registers and copied from one pipeline register to the
following one, until we do not need it any longer. If we try to use TRs that we
had in figure B.1, it is possible that values can be overwritten before all
uses were done. Furthermore, when an instruction moves from the ID stage into
the EX stage of this pipeline implementation, the process of it moving between
the two stages is called issuing. Any instruction that makes this step is
considered to have been issued. In case of MIPS pipeline, all the data hazards
are checked during the ID stage. If there is a data hazard, no issuing happens
as the instruction is being stalled first until it proceeds and can be issued. Consequently,
determining what forwarding technique that will be needed during ID and set the
suitable controls at the right time. This early detection reduces the
complexity of the hardware.